Alchip Unveils AI 3DIC Design and IP Platform

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Showcases packaging and IP integration for next-gen AI functionality

Taipei, Taiwan, Dec. 13, 2023 (GLOBE NEWSWIRE) — Alchip Technologies today revealed that the company presented a paper at the TSMC 2023 Taiwan Open Innovation Platform® Ecosystem Forum showcasing its ground-breaking collaborative advanced artificial intelligence (AI) 3DIC chiplet design and integrated IP methodology.

The paper, entitled “A Case Study Demonstrating the Advantages of 224G Interconnects and 3DIC Architectures for Artificial Intelligence ICs,” provided a detailed explanation of Alchip’s proven design framework, flow and methodology to create a unified platform for die/package exploration, co-design, and analysis. The platform also assembled the bottom die, top die, 3D-APlink interconnects, power and thermal solutions.

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Their revolutionary platform focuses on dramatically increasing the computational power required to handle complex neural networks and large datasets. Traditional architectures struggle to efficiently meet these requirements. But now, advanced SerDes IP technology enables larger scale with 2.5D and 3D package interconnection that consumes less power, occupies a smaller footprint, and operates with greater efficiency.

3DIC integration stores larger, more complex neural networks directly on one chiplet, reducing frequent data transfers to external memory, according to the paper. This enhances computational efficiency, reduces energy consumption, and enables real-time processing of larger datasets.

The 3DIC technology stacks compute dies on top of memory and interconnect dies using high-density through-silicon-vias (TSV) and hyper bumps to increase compute transistor density, larger SRAM die, shorter interconnects, improved power efficiency with minimal latency, the authors said.

The paper envisions combining IP-driven interconnects with 3DIC chiplets to address daunting challenges computational power, memory capacity, and interconnect optimization challenges. AI chip designers are now freed to push the boundaries of AI capabilities, leading to more powerful, efficient, and scalable artificial intelligence systems.

Alchip revealed in the presentation that they designed the 3DIC device using TSMC’s CoWoS® advanced packaging to integrate the advanced SerDes IP. The package design has undergone thorough simulation for signal integrity (SI), power integrity (PI), and thermal considerations. A third-party user provided guidance on package breakout, thermal management, and PI consideration and have successfully completed a comprehensive system design, the paper announced.

For more information, go to www.alchip.com

About Alchip

Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global provider of silicon and design and production services for system companies developing complex and high-volume ASICs and SoCs.  Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technology. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3D package services, CoWoS/chiplet design and manufacturing management. Customers include global leaders in AI, HPC/supercomputer, mobile phones, entertainment device, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661). 

CONTACT: Charles Byers Alchip Technologies + (408)-310-9244 [email protected] 

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